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Senior HW/SW Verification Engineer

Location: Silicon Valley

We're a well funded community of builders - engineers, designers, and entrepreneurs - who love what we do. We are looking for people who share our passion, our drive, our commitment and our abilities. NGCodec is working on the next generation of video compression and we have a $Billion plan to change how the internet uses video. Come join our journey

NGCodec uses a High Level Synthesis (HLS) design methodology, meaning that although we are designing hardware, the design description is in C++ which is automatically synthesized into Verilog RTL by a synthesis tool.  

The primary task is to be responsible for validation of our C++ HW design against a golden reference model, also written in C++.  This involves creating and maintaining a test bench that can compare the behavior of the two designs at a block by block level.  Also, defining tests and coverage strategies, setting up regressions, debugging mismatches,

Although this is essentially a HW verification task, we are not using traditional HW verification EDA tools, and most of the
is purely in C++.  Therefore, this job could be filled by a person with a traditional HW verification background, or also by a SW engineer with a reasonable understanding of HW.

Requirements / Qualifications:

The ideal candidate will have all of the qualifications below.  The first two are mandatory, and the more of the remaining that you can lay claim to, the more favorably we will look upon your resume.

+ 5-10 years of experience in HW verification, OR 5-10 years C++ SW design and debug with some HW background.
+ High degree of proficiency with C++, object oriented programming, inheritance, etc.
+ Experience in video encoding / decoding with H.264 or HEVC or similar
+ Proficiency with Verilog design and debug
+ Scripting with Python, Perl or similar
+ Experience with C++ code coverage tool such as GCov, Bullseye, etc.
+ Adept at working in a Linux development environment
+ Experience with PCIe, either from a HW implementation or firmware development perspective

Please include a cover letter with your application correlating your experience with these qualifications

Compensation:

Industry-competitive salary depending on level of experience
Stock options with four-year vesting
Health insurance
401K
 

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Senior Hardware Digital Design Engineer

Location: Silicon Valley or Toronto or Waterloo

We're a well funded community of builders - engineers, designers, and entrepreneurs - who love what we do. We are looking for people who share our passion, our drive, our commitment and our abilities. NGCodec is working on the next generation of video compression and we have a $Billion plan to change how the internet uses video. Come join our journey.

The person filling this position will play a significant role in implementing our second encoder product.  He/She will be required to engage in diverse activities including C/C++ modeling, HLS (High Level Synthesis), microarchitecture, RTL design, documentation, synthesis for ASIC and FPGA, and verification.  The primary goal is to move our encoder bit accurate C++ model to a hardware implementation.

Responsibilities:

  • Define module level microarchitecture to move our C++ encoder model to a HW implementation

  • Write HLS C++ code (as opposed to RTL) to implement the hardware design

  • In areas where HLS is inappropriate, code Verilog RTL

  • Synthesize, test and debug hardware on FPGA platform

 

Required Skills and Experience:

  • BSEE, MSEE with at least 10 years experience, including multiple chip design projects from inception to tape-out.

  • Experience in defining and implementing a hardware design starting from a written spec and/or software model

  • Expert Verilog RTL designer

  • Proficient C/C++ coder with recent programming experience

 

Desirable Additional Experience:

  • Experience with video encoding and decoding, especially H.264 or H.265

  • Experience with High Level Synthesis

  • Experience with Xilinx or Altera FPGAs, and synthesizing and implementing designs on FPGAs

  • System Verilog and SystemVerilog Assertions

 

Video Codec Algorithm Engineer

Location: Silicon Valley

POSITION: Video Codec Algorithm Engineer

POSITION DESCRIPTION: Develop video compression algorithms using standard compression schemes such as HEVC, AVC, VP9, AV1, and MPEG-2. Develop video processing software for noise removal and high dynamic range video. Optimize and analyze existing video encoder software and develop new features to improve subjective and objective video quality.

EDUCATION REQUIREMENTS: Master’s Degree in Electronics Engineering or foreign educational equivalent.

EXPERIENCE: At least three years of experience as a Video Codec Algorithms Engineer or Principal Video Codec Engineer required.

SPECIAL SKILLS: Requires experience with developing algorithms for adaptive tuning of video encoders for improved PSNR or visual quality; writing low level firmware for control of HW blocks; image processing, especially spacio-temporal noise filtering; and at least three years of experience with H.264 and HEVC encoding standards.

LOCATION: Sunnyvale, CA
Send resumes to NGCodec, Inc., 440 North Wolfe Road, Sunnyvale, CA 94085.