Senior Hardware Digital Design Engineer

Location: Silicon Valley or Waterloo Canada

Position Description

As a Senior ASIC Design Engineer within our small video codec design team, you will be able to contribute to all aspects the digital design process from architecture, to implementation and verification, and into product. You will have the ability to influence and improve our design process through your knowledge of state-of-the-art design methodology.

The Company

NGCodec has asserted itself as the dominant industry leader in video compression, providing products with the highest video quality and ultra-low latency. With the emergence of video content over the internet, our reach extends across the entire globe.  You will become an equity stake holder in a company that has all the benefits of a startup, with an impressive portfolio of investors, and has a growing revenue stream from its customers.

The Team

NGCodec is expanding! We have started an IC Design Centre in Waterloo Canada to complement and collaborate with our experienced team of seasoned video experts in Sunnyvale California. We have a very positive and open work culture. Communication and employee satisfaction are important to us and we are constantly improving our workplace.

Responsibilities:

  • Lead feasibility of new products and the development of chip specification based on customer and marketing requirements

  • Define module level microarchitecture

  • Low power, high density codec hardware design using Verilog/HLS, and verification using C/System Verilog

  • Prototyping on FPGA, Synthesis and Timing closure on ASIC.

  • Preparation of technical reviews and product documentations

Required Skills and Experience:

  • Minimum a Bachelor degree in electrical/computer engineering or equivalent.

  • 8 years minimum of direct experience in industry pertaining to digital IC development.

  • Proven track record of successful silicon designs from concept to working products.

  • CAD tool expertise including logic synthesis, STA, DFT/ATPG, equivalency checking.

  • Proficient C/C++ coder with recent programming experience

  • Ability to automate verification and design tasks with Python, TCL and Makefiles.

  • Ability to operate as digital lead designer for complex digital systems and chips.

  • Self-motivated individual, innovative, confident, thorough and team oriented.

  • Excellent verbal and written communication.

Desirable Additional Experience:

  • Experience with video encoding and decoding, especially H.264/AVC, H.265/HEVC, VP9, AV1.

  • Experience with High Level Synthesis

  • Experience in DSP, microcontrollers and programming in assembly and C

  • Experience with Xilinx Vivado FPGAs, and synthesizing and implementing designs on FPGAs

  • Exposure to ASIC P&R

  • System Verilog and SystemVerilog Assertions

Video Codec Algorithm Engineer

Location: Silicon Valley or Waterloo

We're a well funded community of builders - engineers, designers, and entrepreneurs - who love what we do. We are looking for people who share our passion, our drive, our commitment and our abilities. NGCodec is working on the next generation of video compression and we have a $Billion plan to change how the internet uses video. Come join our journey.

You will also be involved in modeling, architecture and performance enhancements. The group interacts daily with Software, Hardware Designers and Systems teams on a variety of topics including architecture, modeling, video quality and various levels of debugging/verification.  You will be responsible for coordinating certain project activities within the group, performing independent research and will have ownership of specific design areas.

Develop video compression algorithms using standard compression schemes such as HEVC, AVC, VP9, AV1, and MPEG-2. Develop video processing software for noise removal and high dynamic range video. Optimize and analyze existing video encoder software and develop new features to improve subjective and objective video quality. 

Responsibilities:

  • Developing video compression algorithms

 

Required Skills and Experience:

  • Masters or Ph.D. degree in electrical engineering, computer engineering, or computer science

  • 3 years of experience in developing algorithms for video compression systems

  • Direct experience with standard compression schemes, e.g. HEVC/AVC/VP9/AV1/MPEG-2 etc.

  • Experiences with video quality optimization of digital video compression systems

  • Extensive programming experience in C/C++ applied to image/video processing

  • Quick learner and team player with ability to work well in a fast-paced environment

  • Solid programming skills, problem solving and debugging skills

  • Excellent communication skills, (written, and verbal)

 

Desirable Additional Experience:

  • Signal processing, including audio/video processing and/or rate control

  • Experience in HLS, Verilog/VHDL, SystemVerilog, SystemC, Perl/Python

  • Experence of working with semiconductor implementation teams

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Senior HW/SW Verification Engineer

Location: Silicon Valley or Waterloo Canada

We're a well funded community of builders - engineers, designers, and entrepreneurs - who love what we do. We are looking for people who share our passion, our drive, our commitment and our abilities. NGCodec is working on the next generation of video compression and we have a $Billion plan to change how the internet uses video. Come join our journey

NGCodec uses a High Level Synthesis (HLS) design methodology, meaning that although we are designing hardware, the design description is in C++ which is automatically synthesized into Verilog RTL by a synthesis tool.  

The primary task is to be responsible for validation of our C++ HW design against a golden reference model, also written in C++.  This involves creating and maintaining a test bench that can compare the behavior of the two designs at a block by block level.  Also, defining tests and coverage strategies, setting up regressions, debugging mismatches,

Although this is essentially a HW verification task, we are not using traditional HW verification EDA tools, and most of the
is purely in C++.  Therefore, this job could be filled by a person with a traditional HW verification background, or also by a SW engineer with a reasonable understanding of HW.

Requirements / Qualifications:

The ideal candidate will have all of the qualifications below.  The first two are mandatory, and the more of the remaining that you can lay claim to, the more favorably we will look upon your resume.

+ 5-10 years of experience in HW verification, OR 5-10 years C++ SW design and debug with some HW background.
+ High degree of proficiency with C++, object oriented programming, inheritance, etc.
+ Experience in video encoding / decoding with H.264 or HEVC or similar
+ Proficiency with Verilog design and debug
+ Scripting with Python, Perl or similar
+ Experience with C++ code coverage tool such as GCov, Bullseye, etc.
+ Adept at working in a Linux development environment
+ Experience with PCIe, either from a HW implementation or firmware development perspective

Please include a cover letter with your application correlating your experience with these qualifications

Compensation:

Industry-competitive salary depending on level of experience
Stock options with four-year vesting
Health insurance
401K
 

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